Quantum-Tunnelling Based Ultra-Low Voltage Logic Circuits for Edge Devices
DOI:
https://doi.org/10.63282/3050-922X.IJERET-V2I4P113Keywords:
Tunnel Field-Effect Transistor, Band-to-Band Tunneling, Subthreshold Swing, Ultra-Low Voltage Logic, Edge Computing, IoT Circuits, Quantum Tunneling, Near-Threshold Computing, III-V Heterostructure, Energy-Delay Product, Am bipolar Conduction, DPA-Resilient CircuitsAbstract
Tunnel field-effect transistors (TFETs) are promising alternative devices for ultra-low voltage logic in the era of energy constraints that govern the design of edge computing and Internet-of-Thing (IoT) platforms. TFETs take advantage of the quantum mechanical band-to-band tunneling (BTBT) process to transcend this fundamental subthreshold swing (SS) limit of 60 mV/decade at room temperature that is inherent to MOSFETs. The silicon p-i-n TFET structure has been reported to have a reported SS as low as 22 mV/decade, and core-shell nanowire architectures of III-V materials like InAs-GaSb and GaSb-InAs have been demonstrated to achieve ON-state currents of over 300 µA/µm at supply voltages less than 0.5 V. This synthesis covers the theory of quantum tunneling in p-i-n device architecture, the latest circuit topologies and inverters based on the TFET, NAND/NOR gates, static random-access memory (SRAM) cells, and differential power analysis (DPA)-resilient cryptographic circuits. The TFET logic families are compared with silicon, III-V compound, and near-threshold CMOS benchmark devices, and energy-delay products are found to be as low as 10 times that of the CMOS devices at the same supply voltage (< 0.5 V). The ambipolar conduction artifact and low ON-state current of the TFETs, process variations, and forward-bias leakage in p-i-n junctions are addressed, with mitigation strategies validated by circuit-level simulation. The results of this study are taken together as a testimony to the potential of TFETs as a new device technology for sub-0.5-V edge logic by 2020.
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